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CPU Pin Assignments

386SX 386DX (PGA) 486SX ~ DX4 486DX4 ~ 5x86

386SX Pin Assignment

Pin Signal Pin Signal Pin Signal Pin Signal
1 D0 26 LOCK# 51 A2 76 A21
2 Vss 27 NC 52 A3 77 Vss
3 HLDA 28 FLT# 53 A4 78 Vss
4 HOLD 29 NC 54 A5 79 A22
5 Vss 30 NC 55 A6 80 A23
6 NA# 31 NC 56 A7 81 D15
7 READY# 32 Vcc 57 Vcc 82 D14
8 Vcc 33 RESET 58 A8 83 D13
9 Vcc 34 BUSY# 59 A9 84 Vcc
10 Vcc 35 Vss 60 A10 85 Vss
11 Vss 36 ERROR# 61 A11 86 D12
12 Vss 37 PEREQ 62 A12 87 D11
13 Vss 38 NMI 63 Vss 88 D10
14 Vss 39 Vcc 64 A13 89 D9
15 CLK2 40 INTR 65 A14 90 D8
16 ADS# 41 Vss 66 A15 91 Vcc
17 BLE# 42 Vcc 67 Vss 92 D7
18 A1 43 NC 68 Vss 93 D6
19 BHE# 44 NC 69 Vcc 94 D5
20 NC 45 NC 70 A16 95 D4
21 Vcc 46 NC 71 Vcc 96 D3
22 Vss 47 NC 72 A17 97 Vcc
23 M/IO# 48 Vcc 73 A18 98 Vss
24 D/C# 49 Vss 74 A19 99 D2
25 W/R# 50 Vss 75 A20 100 D1

386DX (PGA) Pin Assignment

Pin Signal Pin Signal Pn Signal Pin Signal Pin Signal Pin Signal
A1 Vcc B9 BUSY# D3 A9 H1 A17 L13 D8 N7 Vcc
A2 Vss B10 W/R# D12 Vcc H2 A18 L14 D6 N8 D23
A3 A3 B11 Vss D13 NA# H3 A19 M1 A26 N9 D21
A4 NC B12 NC D14 HOLD H12 D0 M2 A29 N10 D17
A5 Vcc B13 BE2# E1 A14 H13 D1 M3 Vcc N11 D16
A6 Vss B14 Vss E2 A13 H14 D2 M4 Vss N12 D12
A7 Vcc C1 A8 E3 A12 J1 A20 M5 D31 N13 D11
A8 ERROR# C2 A7 E12 BE0# J2 Vss M6 D28 N14 D9
A9 Vss C3 A6 E13 NC J3 Vss M7 Vcc P1 A30
A10 Vcc C4 A2 E14 ADS# J12 Vss M8 Vss P2 Vcc
A11 D/C# C5 Vcc F1 A15 J13 Vss M9 D20 P3 D30
A12 MI/O# C6 NC F2 Vss J14 D3 M10 Vss P4 D29
A13 BE3# C7 NC F3 Vss K1 A21 M11 D15 P5 D26
A14 Vcc C8 PEREQ F12 CLK2 K2 A22 M12 D10 P6 Vss
B1 Vss C9 RESET F13 NC K3 A25 M13 Vcc P7 D24
B2 A5 C10 LOCK# F14 Vss K12 D7 M14 HLDA P8 Vcc
B3 A4 C11 Vss G1 A16 K13 D5 N1 A27 P9 D22
B4 NC C12 Vcc G2 Vcc K14 D4 N2 A31 P10 D19
B5 Vss C13 BE1# G3 Vcc L1 A23 N3 Vss P11 D18
B6 NC C14 BS16# G12 Vcc L2 A24 N4 Vcc P12 D14
B7 INTR D1 A11 G13 READY# L3 A28 N5 D27 P13 D13
B8 NMI D2 A10 G14 Vcc L12 Vcc N6 D25 P14 Vss

486 Pin Assignment

*1
A3 NC TCK NC TCK TCK NC TCK NC
A10 NC NC NC NC ** NC NC SUSPA#
A12 NC NC NC NC NC NC SMI#
NC NC NC NC NC RPLSET1
A14 NC TDI NC TDI TDI NC TDI NC
A15 NMI IGNNE# IGNNE# IGNNE# IGNNE#
B10 NC NC NC SMI# SMI# NC NC
B13 NC NC NC NC
NC TMS TMS TMS TMS
B15 NC NMI NMI NMI NMI
B16 NC TDO NC TDO TDO NC TDO
C3 CLM CLK CLK CLK CLK
C10 NC NC NC SRESET NC NC SMADS
NC NC NC
C12 NC NC NC SMIACT# SMIACT# NC RPLSET0
C13 NC NC NC NC NC NC RPLVAL#
NC NC NC
G15 NC NC NC NC STPCLK# STPCLK# NC SUSP#
J1 VCC VCC VCC5 VCC5 NC NC
NC NC NC NC
S4 NC NC NC VOLDET VOLDET VOLDET VOLDET INVAL
--- --- KEY --- --- KEY --- ---
*1

*1 AMD DX2 3.3V PART *2 to Vss: 2x, NC=Open (Internally Pull-Up): 3x (AMD DX2 5V part does not have CLKMUL pin)

486 Pin Assignment (2)

A3 TCK NC TCK TCK NC TCK
A10 NC ** NC NC INV SUSPA# INVAL
A12 NC NC NC HITM SMI# HITM#
NC NC NC RPLSET1 SUSPA#
A14 TDI NC TDI TDI NC TDI
A15 IGNNE# IGNNE# IGNNE# IGNNE#
B10 SMI# SMI# NC SMI# NC SMI#
B13 NC NC WB/WT NC
TMS TMS TMS TMS
B15 NMI NMI NMI NMI
B16 TDO NC TDO TDO TDO
C3 CLK CLK CLK CLK
C10 SRESET NC NC SRESET SMADS WM_RSET
NC
C12 SMIACT# SMIACT# NC SMIACT RPLSET0 SMADS
C13 NC NC NC NC RPLVAL# NC
NC
G15 STPCLK# STPCLK# NC STPCLK# SUSP# SUSP#
J1 VCC5 VCC5 NC NC NC NC
NC
S4 VOLDET VOLDET VOLDET VOLDET INVAL VOLDET
--- KEY --- ---- ---

*1 AMD DX2 3.3V PART *2 to Vss: 2x, NC=Open (Internally Pull-Up): 3x *3 to Vss: 4x, NC=Open (Internally Pull-Up): 3x

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Content created and/or collected by: Louis F. Ohland, Peter H. Wendt, David L. Beem, William R. Walsh, Tatsuo Sunagawa, Tomáš Slavotínek, Jim Shorney, Tim N. Clarke, Kevin Bowling, and many others.

Ardent Tool of Capitalism is maintained by Tomáš Slavotínek. Last update: 08 May 2024 - Changelog | About | Legal & Contact

COMPUTER POWER SUPPLY: PINOUT, CABLES, CONNECTORS

ATX power supply pinout 24 and 20 pin

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5 Commonly Asked CPU Pin Questions Explained

Disclaimer: This post may contain affiliate links, meaning we get a small commission if you make a purchase through our links, at no cost to you. For more information, please visit our Disclaimer Page .

CPUs are pricey. But despite its small size, it can do a lot of things for your PC. However, it’s fragile and you need to handle it with care. If you plan to assemble your PC or you’re experiencing a problem with your CPU pins, here are answers to some of the commonly asked CPU pin questions.

cpu pin2

Table of Contents

Will CPU work with bent pins?

CPU may or may not work with bent pins. It’s a matter of chance and you’ll know it still works after you run your PC. Many would say that you replace your CPU if you found out that there’s a bent pin on it. But it’s not practical to just throw it away and replace it with a new one.

So, before you throw the CPU away, try to run it first. If it still runs, you’re a lucky one. If not, try to fix it. But before I go in-depth about fixing CPU pins, let me share with you some information on why some bent pins work while some don’t.

Types of CPU pins

CPU pins have different functions, which are divided into different sections. The sections include power, memory, QPI data, and reserved. The sections are not placed in one row. They are scattered within the CPU. It can be two pins for the power memory then the next set in a row is the memory pins. Unless you have a map for the pins, you can easily locate which pin has the problem. Because a CPU you buy doesn’t come with it, checking if the system boot is the easiest way to know if the bent pin still works.

Reasons bent pins don’t work

Bent pins don’t work when it’s disconnected to the other components of the CPU such as memory cards and graphic cards. When the pins are disconnected from these components, the CPU becomes useless. So, buying a new CPU becomes an option.

But even if your CPU pin is not bent or broken, but if it gets corroded, it’ll be useless as well. Giving it a try to fix it is a waste of time. It’s better to buy a new one.

Reasons bent pins work

This is one of the most interesting parts of this topic because you don’t need to buy a new CPU even if it has bent pins. There are two reasons bent pins work. The first reason is that the bent pin is a ground pin that doesn’t have any impact on the entire system when it gets damaged. This is also true for a redundant pin or a pin that is not connected to other components. These pins are included as part of the standard connector but they can be completely unused. If you bend any of these pins, you have no problem at all.

A bent pin with a non-critical function won’t hurt the system. These pins can be connected to a port not used or to a LED. These connections are not significant to run your PC. You may not notice them even if they don’t work.

Fixing a bent pin

To fix a bent pin, you can use a toothpick, credit card, or small screwdriver. You just need to move the pins carefully and try your best to align them with other pins. Be careful when you move the pins because they can snap easily. When it snaps, the CPU may not work again.

Will CPU work with broken pin?

The CPU can still work with a broken pin. It’s the same logic about bent pins where the CPU can still work even though some pins are bent. It’s because the damaged pin has a non-critical function that won’t affect the system. However, if the damaged pin has a critical function, your CPU may lose the signal attached to that line due to broken contact.

Another thing that may happen is that you can see errors or intermittent drops. It usually happens when solder cracks. On the other hand, small cracks cause air gaps that can lead to parasitic capacitance. The cracks can also lead to EMI issues. It happens when there’s a reflectance on an open circuit.

When a pin gets corroded, the CPU can suffer from skin effects. When it occurs, the CPU experiences a line impedance because the signals travel on the inductor’s skin.

Can bent pins damage the CPU?

Bent pins can damage the CPU especially when it makes contact with other pins. The contact may become dangerous when the bent pin touches a pin that carries a current. It can catch fire that may damage the other component such as the motherboard.

What problems can it cause?

A bent pin may not catch fire all the time. It depends on the pin’s function and the electrical connection. If the pin is used for giving signals, your PC can experience electrical issues. In effect, the system becomes unstable.

When a pin is bent, a CPU may not be able to send data, which disables other functions where it should send the data. You experience dead PCI slots, dead memory slots, and dead peripherals. When the data is disabled, your CPU can’t be able to receive or transmit data.

Apart from the effects mentioned, when there’s a bent pin a delay happens when you turn on your PC. You can notice that your PC is not posting initially. There are times when you get an FF code when you try to post. If you’re unlucky, your PC will experience a total failure to boot.

Are CPU pins gold?

CPU pins are gold-plated. They are not solid gold. It’s used in electronics because it has better properties than silver and copper. Although silver and copper are better conductors than gold, they are more reactive. Even with a small amount of humidity, silver and copper oxidize in the environment. Because of the cons of these elements, gold is used, instead.

Gold has different chemical properties perfect for CPU pins. It’s corrosion-resistant so it doesn’t tarnish even if it gets exposed to the atmosphere. When it’s alloyed with other elements, it becomes wear-resistant and stronger.

If you’re thinking that you can get gold from broken pins, I’m sorry to burst your bubble, it won’t work. You can’t get solid gold on a CPU pin.

cpu pin

Do all CPUs have pins?

Some CPUs have pins while others don’t have them. It depends on the configuration of the CPU. There are two types of configuration such as LGA and PGA. These configurations dictate where you can find the pins.

LGA or the Land Grid Array is common for the latest versions of Intel CPUs. In this configuration, the pins are located on the motherboard and the CPU has metal pads. LGA is safer to use because there’s no pin to break on your CPU. Although it’s hard to fix a broken pin on a motherboard, it’s less likely to break easily than when the pin is placed on the CPU.

On the other hand, the PGA or Pin Grid Array has pins on the CPU. The downside of this configuration is it can break easily after three years of usage. If you plan to replace your cooler at this time, you need to be careful because some pins might bend when you remove the CPU from the socket. During this time, the CPU paste may not be as sticky as it was so you may rip out the CPU pins.

When your CPU pin bends or breaks, don’t panic. Try to run your PC and see if it boots. If it works, you don’t have a problem. If it doesn’t, try fixing the pins before you buy a new CPU. You can also opt for the LGA configuration if you think you’re too clumsy to handle a CPU.

Related posts:

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cpu pin assignment

Byte Bite Bit

How Many Pins Does a CPU Have: Unveiling Processor Pin Counts

When we talk about a CPU, or central processing unit, discussing pin count is essential because it determines how a CPU interfaces with the motherboard. Historically, the number of pins on a CPU has varied greatly. For instance, older processors typically had fewer pins, with some having just a couple hundred. Modern CPUs, however, often have much more complex pin configurations that can run into the thousands. These pins are crucial for electrical connectivity and ensuring that the processor can communicate effectively with other parts of the computer, such as RAM and storage.

How Many Pins Does a CPU Have: Unveiling Processor Pin Counts

Knowing the pin count is particularly important when upgrading or building a computer, as CPUs must match their corresponding socket on the motherboard. Intel and AMD, the two main CPU manufacturers, use different socket types and, thus, different pin counts. For example, Intel’s LGA 1151 CPUs have 1151 pins, while the LGA 1200 CPUs come with 1200 pins. Similarly, AMD’s AM4 CPUs are equipped with 1331 pins. Each pin has a specific role in power delivery, data transmission, or grounding.

CPU socket types further define pin configurations and include Land Grid Array (LGA), Pin Grid Array (PGA), and Ball Grid Array (BGA). Each of these socket types has a different method of connecting the CPU to the motherboard. LGA sockets, for instance, contain pins on the socket itself and contact points on the CPU, while PGA sockets have the reverse, with pins on the CPU that insert into holes on the socket. BGA sockets are used for permanently mounted CPUs that are not intended to be removed or upgraded, making them less common for consumer-level computer systems.

  • 1.1 Pin Functions
  • 1.2 Pin Counts and CPU Models
  • 2.1 Intel Socket Types
  • 2.2 AMD Socket Types
  • 3.1 Avoiding CPU Pin Damage
  • 3.2 Correct CPU Insertion Techniques
  • 4.1 Historical Developments
  • 4.2 Future Trends

CPU Pin Basics

In assessing the fundamental aspects of CPU pins, it’s crucial to understand their roles and variations across different processor models and sockets. We’ll explore the specific purposes these pins serve and how their counts differ with CPU sockets.

A CPU with numerous pins arranged in a grid pattern on its underside

Pin Functions

Pin counts and cpu models.

Intel® Core™, Pentium®, Celeron® (6th & 7th Gen) N/A
Intel® Core™, Pentium®, Celeron® (10th & 11th Gen) N/A
N/A Ryzen™ 1000, 2000, 3000, 5000 series
N/A Future Ryzen™ models

We notice that pin count varies by socket type and CPU model. For example, Intel’s LGA 1151 socket supports CPUs with 1151 pins, whereas the LGA 1200 has 1200 pins. AMD’s latest AM4 socket accommodates CPUs with 1331 pins. These differences reflect technological advancements and are tailored to the architecture of each CPU model.

CPU Socket Compatibility

With a range of sockets available, it’s crucial to understand which CPUs and motherboards are compatible. Intel and AMD, the two major players in the market, offer various sockets with distinct pin configurations.

Intel Socket Types

2015 1151
2020 1200
2017 2066

AMD Socket Types

AMD uses the PGA (Pin Grid Array) design wherein the pins are located on the CPU. The widely adopted AM4 socket supports most AMD Ryzen processors. The AM4 socket offers broad compatibility across a range of CPUs, which is beneficial for users looking for an upgrade without changing the entire motherboard. AMD’s commitment to keeping support for the AM4 socket across multiple CPU generations has been a strong selling point for their processors.

2016 1331
Socket A 1999 462

Installation and Handling of CPU Pins

Handling CPU pins requires precision and care, as they are critical to a CPU’s functionality and are incredibly fragile. In this section, we’ll guide you through avoiding damage to CPU pins and the correct techniques for inserting a CPU.

Avoiding CPU Pin Damage

Correct cpu insertion techniques.

The precise alignment of CPU pins with the socket holes is essential for a successful installation. Most CPUs use a pin design that complements the socket, ensuring correct orientation. The CPU often has an arrow or a corner mark to indicate the proper alignment.

Step Action Details
Look for a triangle or mark on the CPU corner. This aligns with a similar mark on the socket.
Carefully lift the retaining lever on the socket. Prepare the socket to receive the CPU.
Gently align and place the CPU into the socket. Do not use force; the CPU should settle naturally.
Lower the lever This locks the CPU in place.

Once the CPU sits comfortably in the socket without any force, secure it by closing the lever. Applying too much force or incorrect alignment can result in damaged pins that may render the CPU or motherboard unusable. Always refer to the manufacturer’s guide for instructions specific to your CPU and motherboard.

Evolution of CPU Sockets and Pins

The way processors connect to motherboards has significantly changed over time, with advancements leading to variations in the number and layout of pins. We’ll explore the historical advancements and speculate on future trends in CPU socket and pin technology.

Historical Developments

Future trends, related posts:.

  • Be Quiet vs Noctua: Which Fan Is Much Better for Your PC?
  • Best CPU Cooler for I7 8700K: The CPU Coolers That No Will Tell You
  • Are i3 CPUs Good for Budget Computing? Assessing Value and Performance
  • Best CPU GPU Combos for Gaming 1080p, 1440p, 4k: Performance Pairings for Every Resolution
  • Can a CPU Survive a Drop: Assessing Impact Resistance in Processors
  • Can CPUs Go Bad? Understanding Processor Failures and Lifespan
  • Can You Install Windows 11 with Unsupported CPU: Unveiling Potential Workarounds
  • How to Tell if Laptop CPU is Soldered: Identifying Integrated Processors
  • Idle Temperature for CPU: Understanding Safe Ranges and Benchmarks
  • Is Undervolting CPU Safe: Risks and Benefits Explained
  • How to Monitor CPU GPU Temperature: Essential Tracking Tips for Your PC
  • What Does Processor Count Mean: Understanding CPU Cores and Performance

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Performance Improvements in VMs by adjusting CPU pinning and assignment

dlandon

By dlandon May 12, 2016 in VM Engine (KVM)

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There have been several posts on the forum about VM performance improvements by adjusting CPU pinning and assignments in cases of VMs stuttering on media playback and gaming.  I've put together what I think is the best of those ideas.  I don't necessarily think this is the total answer, but it has helped me with a particularly latency sensitive VM.

Windows VM Configuration

You need to have a well configured Windows VM in order to get any improvement with CPU pinning.  Have your VM configured as follows:

  • Set machine type to the latest i440fx..
  • Boot in OVMF and not seaBIOS for Windows 8 and Windows 10.  Your GPU must support UEFI boot if you are doing GPU passthrough.
  • Set Hyper-V to 'yes' unless you need it off for Nvidia GPUs.
  • Don't initially assign more that 8 GB of memory and set 'Initial' and 'Max' memory at the same value so memory ballooning is off.
  • Don't assign more than 4 CPUs total.  Assign CPUs in pairs to your VM if it supports Hyperthreading.
  • Be sure you are using the latest GPU driver.
  • I have had issues with virtio network drivers newer than 0.1.100 on Windows 7.  Try that driver first and then update once your VM is performing properly.

Get the best performance you can by adjusting the memory and CPU settings.  Don't over provision CPUs and memory.  You may find that the performance will decrease.  More is not always better.

If you have more than 8GB of memory in your unRAID system, I also suggest installing the 'Tips and Tweaks' plugin and setting the 'Disk Cache' settings to the suggested values for VMs.  Click the 'Help' button for the suggestions.  Also set 'Disable NIC flow control' and 'Disable NIC offload' to 'Yes'.  These settings are known to cause VM performance issues in some cases.  You can always go back and change them later.

Once you have your VM running correctly, you can then adjust CPU pinning to possibly improve the performance.  Unless you have your VM configured as above, you will probably be wasting your time with CPU pinning.

What is Hyperthreading?

Hyper threading is a means to share one CPU core with multiple processes.  The architecture of a hyperthread core is a core and two hyperthreads.  It looks like this:

HT ---- core ---- HT

It is not a base core and a HT:

core ---- HT

When isolating CPUs, the best performance is gained by isolating and assigning both pairs for a VM, not just what some think as the '"core".

Why Isolate and Assign CPUs

Some VMs suffer from latency because of sharing the hyperthreaded cpus.  The method I have described here helps with the latency caused by cpu sharing and context switching between hyperthreads.

If you have a VM that is suffering from stuttering or pauses in media playback or gaming, this procedure may help.  Don't assign more cpus to a VM that has latency issues.  That is generally not the issue.  I also don't recommend assigning more than 4 cpus to a VM.  I don't know why any VM needs that kind of horsepower.

In my case I have a Xeon 4 core processor with Hyperthreading.  The CPU layout is:

The Hyperthread pairs are (0,4) (1,5) (2,6) and (3,7).  This means that one core is used for two Hyperthreads.  When assigning CPUs to a high performance VM, CPUs should be assigned in Hyperthread pairs.

I isolated some CPUs to be used by the VM from Linux with the following in the syslinux configuration on the flash drive:

This tells Linux that the physical CPUs 2,3,6 and 7 are not to be managed or used by Linux.

There is an additional setting for vcpus called 'emulatorpin'.  The 'emulatorpin' entry puts the emulator tasks on other CPUs and off the VM CPUs.

I then assigned the isolated CPUs to my VM and added the 'emulatorpin':

What ends up happening is that the 4 logical CPUs (2,3,6,7) are not used by Linux but are available to assign to VMs.  I then assigned them to the VM and pinned emulator tasks to CPUs (0,4).  This is the first CPU pair.  Linux tends to favor the low numbered CPUs.

Make your CPU assignments in the VM editor and then edit the xml and add the emulatorpin assignment.  Don't change any other CPU settings in the xml.  I've seen recommendations to change the topology:

Don't make any changes to this setting.  The VM manager does it appropriately.  There is no advantage in making changes and it can cause problems like a VM that crashes.

This has greatly improved the performance of my Windows 7 Media Center VM serving Media Center Extenders.

I am not a KVM expert and this may not be the best way to do this, but in reading some forum posts and searching the internet, this is the best I've found so far.

I would like to see LT offer some performance tuning settings in the VM manager that would help with these settings to improve performance in a VM without all the gyrations I've done here to get the performance I need in my VM.  They could at least offer some 'emulatorpin' settings.

Note: I still see confusion about physical CPUs, vcpus, and hyperthreaded pairs.  CPU pairs like 3,7 are two threads that share a core.  It is not a core with a hyperthread.

When isolating and assigning CPUs to a VM, do it in pairs.  Don't isolate and assign one (3) and not its pair (7) unless you don't assign 7 to any other VM.  This is not going to give you what you want.

vcpus are relative to the VM only.  You don't isolate vcpus, you isolate physical CPUs that are then assigned to VM vcpus.

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There have been several posts on the forum about VM performance improvements by adjusting CPU pinning and assignments in cases of VMs stuttering on media playback and gaming.  I've put together what I

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I've started working on enhancing the VM Form Editor in my spare time to add extra support for the CPU block so these tweaks we're making can be applied without manually editing the XML.   U

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cpu pin assignment

SpaceInvaderOne

Thats interesting.

I did some testing a few days ago pinning hyperthreaded pairs then pinning none hyperthreaded pairs and running passmark cpu benchmark software afterwards

this is my results using a 12 core xeon @ 2.4ghz 

Using 8 threads or 4 cpu cores

firstly 8 threads  with paired hyperthreads  the passmark score is    7256

next  8 threads  all from non paired separate so one thread from different core passmark score is 10417

I as the threads were all on separate cores the speed was faster but i guess wouldnt have been if the other thread on each core was being used by another process.

I know this is a bit off topic but thought it interesting as i never expected this result

Thats interesting. I did some testing a few days ago pinning hyperthreaded pairs then pinning none hyperthreaded pairs and running passmark cpu benchmark software afterwards   this is my results using a 12 core xeon @ 2.4ghz    Using 8 threads or 4 cpu cores   firstly 8 threads  with paired hyperthreads  the passmark score is    7256 next  8 threads  all from non paired separate so one thread from different core passmark score is 10417   I as the threads were all on separate cores the speed was faster but i guess wouldnt have been if the other thread on each core was being used by another process.   I know this is a bit off topic but thought it interesting as i never expected this result

This is exactly what I would expect in this situation where you are testing maximum speed.  8 cores will be faster than 4 cores with Hyperthreading.  If the cores are being used by other processes, you will see a passmark decrease.  In your first case, you were actually sharing the 4 cores with yourself.

meep

That's interesting indeed as I'm trying to improve performance of a specific VM for gaming.

Is there a reference or technique for determining which pairs match? I have an AMD FX Piledriver and a quick google didn't reveal much of use.

That's interesting indeed as I'm trying to improve performance of a specific VM for gaming.   Is there a reference or technique for determining which pairs match? I have an AMD FX Piledriver and a quick google didn't reveal much of use.   Thanks

The unRaid dashboard shows the paired CPUs.

    The unRaid dashboard shows the paired CPUs.

Superhandy, washed over me completely!

Will check that out when I get home!

There have been several posts on the forum about VM performance improvements by adjusting CPU pinning and assignments in cases of VMs stuttering on media playback and gaming.  I've put together what I think is the best of those ideas.  I don't necessarily think this is the total answer, but it has helped me with a particularly latency sensitive VM.   In my case I have a Xeon 4 core processor with Hyperthreading.  The CPU layout is:   0,4 1,5 2,6 3,7   The Hyperthread pairs are (0,4) (1,5) (2,6) and (3,7).  This means that one core is used for two Hyperthreads.  When assigning CPUs to a high performance VM, CPUs should be assigned in Hyperthread pairs.   I isolated some CPUs to be used by the VM from Linux with the following in the syslinux configuration on the flash drive:   append isolcpus=2,3,6,7 initrd=/bzroot   This tells Linux that the physical CPUs 2,3,6 and 7 are not to be managed or used by Linux.  

So can they be pinned to dockers or only vms after isolocpus

I don't know.  I've not tried.

I emailed the limetech guys about this and thought i would post what they replied in case others are interested.

isolcpus prevents the host OS from assigning the logical CPUs specified in the parameter to any processes (kernel or user space) at boot.  Users can manually assign processes back to those CPUs using Linux's cpuset capabilities.  Docker and virtual machines both support this.  So you can use isolcpus to reserve a set of logical CPUs and then assign docker containers to some and VMs to others and leave the unisolated CPUs for host-based tasks, if you so desire.  There may be some advantages to this, there may be some disadvantages to this.

With respect to adding isolcpus capability post-boot, so that you can toggle its usage on and off, that is an interesting concept that we have been investigating, but it's not something that's built into Linux's capability set today just yet.  We could manually manipulate some things in the user space for this, but it's not something we're tackling as a project right now.

There have been several posts on the forum about VM performance improvements by adjusting CPU pinning and assignments in cases of VMs stuttering on media playback and gaming.  I've put together what I think is the best of those ideas.  I don't necessarily think this is the total answer, but it has helped me with a particularly latency sensitive VM.   In my case I have a Xeon 4 core processor with Hyperthreading.  The CPU layout is:   0,4 1,5 2,6 3,7   The Hyperthread pairs are (0,4) (1,5) (2,6) and (3,7).  This means that one core is used for two Hyperthreads.  When assigning CPUs to a high performance VM, CPUs should be assigned in Hyperthread pairs.   I isolated some CPUs to be used by the VM from Linux with the following in the syslinux configuration on the flash drive:   append isolcpus=2,3,6,7 initrd=/bzroot   This tells Linux that the physical CPUs 2,3,6 and 7 are not to be managed or used by Linux.   There is an additional setting for vcpus called 'emulatorpin'.  The 'emulatorpin' entry puts the emulator tasks on other CPUs and off the VM CPUs.   I then assigned those CPUs to my VM and added the 'emulatorpin':     <cputune>     <vcpupin vcpu='0' cpuset='2'/>     <vcpupin vcpu='1' cpuset='3'/>     <vcpupin vcpu='2' cpuset='6'/>     <vcpupin vcpu='3' cpuset='7'/>     <emulatorpin cpuset='0,1,4,5'/>   </cputune>   What ends up happening is that the 4 physical CPUs (2,3,6,7) are not used by Linux but are available to assign to VMs.  I then assigned them to the VM and pinned emulator tasks to the other CPUs (0,1,4,5).   This has greatly improved the performance of my Windows 7 Media Center VM serving Media Center Extenders.   I am not a KVM expert and this may not be the best way to do this, but in reading some forum posts and searching the internet, this is the best I've found so far.   I would like to see LT offer some performance tuning settings in the VM manager that would help with these settings to improve performance in a VM without all the gyrations I've done here to get the performance I need in my VM.  They could at least offer some 'emulatorpin' settings.

Thankyou dlandon for that excellent info. I have isolcpu 8 cores for my vms and left the rest for unraid and dockers and pinned emulator tasks to 2 of those cores.

Wow i get an extra 1000 score running geek bench3 on my osx vm. And i get no latency on my windows 10 vm.

:)

This needs to be stickied. How do we do the same for Dockers? Does the set-cpu command work?

Squid

How do we do the same for Dockers? Does the set-cpu command work?

http://lime-technology.com/forum/index.php?topic=36257.0

Yes should be stickied!

Yes dockers can be pinned aswell.

click the advanced view then add to extra parameters 

The cpus can be pinned if you have or havent used isolcpus. I dont pin to isolcpus cores myself just to the ones used by unraid, i just avoid pinning dockers to the first pair of threads as i have heard the linux os prefers these itself.

Edit.....oops sorry squid see you just replied before me!!

wedge22

Wow this is great information, thanks for taking the time to investigate as I have noticed significant differences when using previous CPU pinning options. I have a 5930k and if I try to isolate 1,7,2,8 and then assign them to the Windows 10 VM I notice considerable stutter in games and on Youtube, if I change this to 4 physical cores ie 1,2,3,4 then the issues no longer occur. I did not use cores 0, 6 as I have also heard that unRAID prefers these cores. I am going to test out the new method you have posted and will report back.

I'm also noticing stutter when i pin the HT CPUs, will experiment more later...

not pinning the ht cores fixed my problems with fps drops in games! i can now play gta v (3440x1440, ultra settings, fxaa, no msaa/txaa) at ~35-45 fps (before only ~20-30 fps)
  • 2 weeks later...

Robj has stickied this thread, so hopefully it will be easier to find.

I am reconsidering my position on emulator pinning cpus and I am doing some testing right now to see if my idea has merit.  If it does, I will suggest a VM manager change to LT that is very straight forward that will help people get through this without so many gyrations.

If someone wants help in assigning cpus please post the following information and I will make recommendations on your setup.

  • Post your cpu pairing from the dashboard.
  • List your VMs and what each VM is doing.
  • Any issues you are having with VMs as far as performance and stuttering or choppy performance.

I will review and make recommendations about how to set up your configuration.

:o

If I recall the post, he was referring to only using one of the cpu pairs and letting the other be unassigned.  I believe it looked like this:

Isolate 2,3,6,7

Assign 2,3 to the VM and leave 6 and 7 unassigned.

That would leave only one hyperthread running and the other idle.  That would mean that there would not be any context switching delays between cpu pairs 2,3 and 6,7.

This could in theory work to reduce latency, but I'm not sure that is generally necessary.

I've changed the OP to reflect some new thinking I have about the emulator pinning.  I think that it would be best to pin the emulator cpus to only the first cpu pair.  In fact I am thinking all VMs should have the emulator cpus pinned to the first cpu pair.

I have done this for both my VMs and it is working quite well.

I am thinking that we should not pin any VM cpus to the first pair and leave those for Linux, unRAID, and emulator cpus.

Let me know if pinning the emulator cpus only to the first cpu pair works for you.

Ryoko

Hey dlandon, I had a quick question about the emulator pinning.

I have all the other pairs (sans 0,1,8,9) isolated in the syslinux config.

I'm currently using this xml for the VM in question.

Could I emulator pin more pairs using something like this?

Bit of a side note; I've also noticed that though 1,9 isn't explicitly assigned to anything, that it idles around 2200/2200MHz since I isolated and pinned the other cpus. Normally they all rest at 1200/1200MHz.

I've read something about disabling hyperthreading may solve some problems regarding latency. Is that done in BIOS?

What performance gain/loss will that result in? Someone said 10% gain in using hyperthreading?

Then I guess just 6 cpus will show up, instead of 12 in my system, and it makes pinning and assignment somewhat easier to manage.

I've read something about disabling hyperthreading may solve some problems regarding latency. Is that done in BIOS?   What performance gain/loss will that result in? Someone said 10% gain in using hyperthreading?   Then I guess just 6 cpus will show up, instead of 12 in my system, and it makes pinning and assignment somewhat easier to manage.

Yes, you can disable HT in the BIOS!

Hey dlandon, I had a quick question about the emulator pinning.   I've noticed on my system that the Dashboard's System Status in the unRAID webGUI can frequently show the first pair (0, topping out at 2400/2400MHz on my 8 core xeon. I know that you recommended using only the first pair for emulator pinning (even with multiple VMs), but I was curious if it's possible to emulator pin more than one pair per VM? Also, what would the xml for a VM like that look like?   I have all the other pairs (sans 0,1,8,9) isolated in the syslinux config. I'm currently using this xml for the VM in question. <emulatorpin cpuset='0,8'/>   Could I emulator pin more pairs using something like this? <emulatorpin cpuset='0,1,8,9'/>   Bit of a side note; I've also noticed that though 1,9 isn't explicitly assigned to anything, that it idles around 2200/2200MHz since I isolated and pinned the other cpus. Normally they all rest at 1200/1200MHz.

Linux tends to favor the low numbered cpus, so I would expect the first pair would be loaded more.  My recommendation is based on an idea I have presented to LT as a feature request to emulator pin the first pair in all VMs using the VM manager.  The idea is that in a lot of cases doing this would remove latency from some VMs and cut down on the the gyrations needed to get VMs running better.  I was looking for feedback like yours to see if my recommendation has merit.

Yes, you can emulatorpin other cpus.  I have been unable to find anything on the internet about how much load the emulator tasks on a VM load cpus, but my gut feel is not much.

Linux will use additional cpus as it needs them, so any that are not isolated will be available for Linux.

Don't get too concerned about cpu frequency.  The cpu scaling driver/governor that adjusts the cpu frequency can switch up the cpu frequency under a relatively small load.  The Intel pstate driver I am using on my Xeon will ramp up to full speed under a 10-15% load.  Full speed on a cpu does not necessarily mean it is fully loaded.

I have been unable to find anything on the internet about how much load the emulator tasks on a VM load cpus, but my gut feel is not much.

Maybe it could be tested by isolating 1 or 2 cores and assign them only to the emulatorpin and see how much usage the VM does?

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  • Intel's CPU instability and crashing issues also impact mainstream 65W and higher 'non-K' models — damage is irreversible, no planned recall

LGA 1151 Socket pin arrangement

  • Thread starter krb1945
  • Start date Jun 26, 2016
  • Motherboards

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  • Jun 26, 2016

cpu pin assignment

It's because you are using the address to the page and not the image. http://i44.photobucket.com/albums/f30/Ken468/DSC01461_zpsggx4tgqo.jpg

BadActor

No picture attached, but all pins should be straight up and in perfect rows in both axis. You can upload your photo to TinyPics and copy and paste the IMG code in your post.  

Lga pins are not exactly straight like pga pins. The pic is there and you are fine. You can also google socket images btw. https://www.google.com/search?q=lga+1151&espv=2&biw=1920&bih=955&site=webhp&source=lnms&tbm=isch&sa=X&ved=0ahUKEwiS3IuAzcbNAhXDdSYKHQuYDXwQ_AUICCgD&dpr=1  

cpu pin assignment

It's because you are using the address to the page and not the image. http://i44.photobucket.com/albums/f30/Ken468/DSC01461_zpsggx4tgqo.jpg  

  • Jun 27, 2016

I hate getting old... many times I just can't see for looking. I put the socket under the magnifier and it looks like the one pin opposite the hinge has bent over backward. I'm going to order another mobo, then get a higher power magnifier and see if I can repair this one for later use. A delicate task I know, but I've straightened other type contacts before. Some were successes and some failures... I've always been taught you never give up and you accomplish nothing without effort. I sure appreciate the help with both the information and the photo attachment difficulties. To bad y'all don't live in S. Ga. I'd invite all to Angus tenderloin steaks and beer. Top of the day to everyone. Ken  

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What is the Pin Assignment?

3-Pin Connector Pinout

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Pin diagram of 8086 microprocessor is as given below: 

cpu pin assignment

Intel 8086 is a 16-bit HMOS microprocessor. It is available in 40 pin DIP chip. It uses a 5V DC supply for its operation. The 8086 uses a 20-line address bus. It has a 16-line data bus. The 20 lines of the address bus operate in multiplexed mode. The 16-low order address bus lines have been multiplexed with data and 4 high-order address bus lines have been multiplexed with status signals. 

AD0-AD15: Address/Data bus. These are low order address bus. They are multiplexed with data. When AD lines are used to transmit memory address the symbol A is used instead of AD, for example A0-A15. When data are transmitted over AD lines the symbol D is used in place of AD, for example D0-D7, D8-D15 or D0-D15. 

A16-A19: High order address bus. These are multiplexed with status signals. 

S2, S1, S0: Status pins. These pins are active during T4, T1 and T2 states and is returned to passive state (1,1,1 during T3 or Tw (when ready is inactive). These are used by the 8288 bus controller for generating all the memory and I/O operation) access control signals. Any change in S2, S1, S0 during T4 indicates the beginning of a bus cycle.  

S2 S1 S0 Characteristics
0 0 0 Interrupt acknowledge
0 0 1 Read I/O port
0 1 0 Write I/O port
0 1 1 Halt
1 0 0 Code access
1 0 1 Read memory
1 1 0 Write memory
1 1 1 Passive state

A16/S3, A17/S4, A18/S5, A19/S6 : The specified address lines are multiplexed with corresponding status signals. 

A17/S4 A16/S3 Function
0 0 Extra segment access
0 1 Stack segment access
1 0 Code segment access
1 1 Data segment access

HE’/S7: Bus High Enable/Status. During T1 it is low. It is used to enable data onto the most significant half of data bus, D8-D15. 8-bit device connected to upper half of the data bus use BHE (Active Low) signal. It is multiplexed with status signal S7. S7 signal is available during T2, T3 and T4. 

RD’: This is used for read operation. It is an output signal. It is active when low. 

READY : This is the acknowledgement from the memory or slow device that they have completed the data transfer. The signal made available by the devices is synchronized by the 8284A clock generator to provide ready input to the microprocessor. The signal is active high(1). 

INTR : Interrupt Request. This is triggered input. This is sampled during the last clock cycles of each instruction for determining the availability of the request. If any interrupt request is found pending, the processor enters the interrupt acknowledge cycle. This can be internally masked after resulting the interrupt enable flag. This signal is active high(1) and has been synchronized internally. 

NMI : Non maskable interrupt. This is an edge triggered input which results in a type II interrupt. A subroutine is then vectored through an interrupt vector lookup table which is located in the system memory. NMI is non-maskable internally by software. A transition made from low(0) to high(1) initiates the interrupt at the end of the current instruction. This input has been synchronized internally. 

INTA : Interrupt acknowledge. It is active low(0) during T2, T3 and Tw of each interrupt acknowledge cycle. 

MN/MX’ : Minimum/Maximum. This pin signal indicates what mode the processor will operate in. 

RQ’/GT1′, RQ’/GT0′ : Request/Grant. These pins are used by local bus masters used to force the microprocessor to release the local bus at the end of the microprocessor’s current bus cycle. Each of the pin is bi-directional. RQ’/GT0′ have higher priority than RQ’/GT1′. 

LOCK’ : Its an active low pin. It indicates that other system bus masters have not been allowed to gain control of the system bus while LOCK’ is active low(0). The LOCK signal will be active until the completion of the next instruction. 

TEST’ : This examined by a ‘WAIT’ instruction. If the TEST pin goes low(0), execution will continue, else the processor remains in an idle state. The input is internally synchronized during each of the clock cycle on leading edge of the clock. 

CLK : Clock Input. The clock input provides the basic timing for processing operation and bus control activity. Its an asymmetric square wave with a 33% duty cycle. 

RESET : This pin requires the microprocessor to terminate its present activity immediately. The signal must be active high(1) for at least four clock cycles. 

Vcc : Power Supply( +5V D.C.) 

GND : Ground 

QS1,QS0 : Queue Status. These signals indicate the status of the internal 8086 instruction queue according to the table shown below:

QS1 QS0 Status
0 0 No operation
0 1 First byte of op code from queue
1 0 Empty the queue
1 1 Subsequent byte from queue

M/IO’: This signal is used to distinguish between memory and I/O operations. The M Signal is Active high whereas the IO’ Signal is Active Low. When this Pin is High, the memory operations takes place. On the other hand, when the Pin is low, the Input/Output operations from the peripheral devices takes place.  

=DT/R : Data Transmit/Receive. This pin is required in minimum systems, that want to use an 8286 or 8287 data bus transceiver. The direction of data flow is controlled through the transceiver. 

DEN: Data enable. This pin is provided as an output enable for the 8286/8287 in a minimum system which uses transceiver. DEN is active low(0) during each memory and input-output access and for INTA cycles. 

HOLD/HOLDA: HOLD indicates that another master has been requesting a local bus .This is an active high(1). The microprocessor receiving the HOLD request will issue HLDA (high) as an acknowledgement in the middle of a T4 or T1 clock cycle. 

ALE : Address Latch Enable. ALE is provided by the microprocessor to latch the address into the 8282 or 8283 address latch. It is an active high(1) pulse during T1 of any bus cycle. ALE signal is never floated, is always integer. 

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Pin assignments

Moderators: jsmcortina , muythaibxr

Post by jeffmarsh750 » Sun May 29, 2022 8:29 pm

Re: Pin assignments

Post by Six_Shooter » Sun May 29, 2022 8:47 pm

Post by jeffmarsh750 » Sun May 29, 2022 9:45 pm

Six_Shooter wrote: ↑ Sun May 29, 2022 8:47 pm Some pins are CPU pins and will need internal jumpers/circuits in order to be used.

Post by jeffmarsh750 » Sun May 29, 2022 9:50 pm

Post by jeffmarsh750 » Sun May 29, 2022 10:00 pm

jeffmarsh750 wrote: ↑ Sun May 29, 2022 9:45 pm Six_Shooter wrote: ↑ Sun May 29, 2022 8:47 pm Some pins are CPU pins and will need internal jumpers/circuits in order to be used.

Post by LAV1000 » Mon May 30, 2022 8:37 am

Post by rickb794 » Wed Jun 01, 2022 10:15 am

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motherboard connector pin assignment

Dell dimension 9200 fan pins and signals.

cpu pin assignment

  • Ask a question
Pin
Number
Pin
Name
Description
1 Sense

yellow or white // from fan

2 12 V red // fix voltage
3 GND black
4 Speed blue or green // from mainboard
5 NC  unused

Measurements with CPU heat of 40°C:

Sense puls: ca. 27 Hz ( duty cycle 50:50), 3.3 V

Speed puls: ca. 2 usec and 43 usec pause, 3.3 V; probably a pwm puls

The fans that connect to the header are: Model AFC1212DE , DELL PIN: MJ989.

DELL Dimension 9200 Fan diagram

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Building a pc here's how to save on the cpu.

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Why Are PC Builders Using "Dummy" RAM?

Samsung now sells 1tb microsd cards, 3 reasons all phones should have two usb-c ports, quick links, consider refurbished or used cpus, get an older cpu, buy a cpu that comes with (or without) a cooler, ignore the brand, skip (or get) integrated graphics, hunt for bundles and sales, account for future-proofing, key takeaways.

  • Consider buying used or refurbished CPUs for significant savings without sacrificing performance and longevity.
  • Opt for slightly older CPU models for substantial value and performance while saving money.
  • Don't focus on brand; compare performance and price for the best CPU option.

The CPU is the main processing unit of your computer, so you want to get a decent one that can serve you for years to come. That being said, it's easy to overspend on the CPU, so I'll share with you a few tips on how to buy the best CPU for the least amount of cash.

One of the best ways to save hundreds of dollars on your CPU is to buy a used one. Enthusiasts who always want the latest and greatest flood the used market with previous-gen CPUs en masse when a new generation drops. This is a great opportunity for you, as you can get a slightly older CPU for pennies on the dollar.

Used CPUs are generally a safe purchase , as CPUs can easily outlast their usefulness. Generally speaking, if a CPU works out of the box and doesn't have a factory error, it'll continue to work for many years to come. Even if the CPU was overclocked, a mild overclock is unlikely to have done any permanent damage. I've been rocking overclocked CPUs since 2017, and I have yet to see one die on me.

This being said, if you have a chance to test the CPU in person before purchasing it, do so by running a stress test and monitoring the temperature. You can never know if someone is trying to sell you a broken chip.

Refurbished chips are slightly safer, but they're not without issues. I once purchased a refurbished AMD Ryzen 7 2700X, and it arrived with a bunch of bent pins, as AMD CPUs used the PGA layout up to the Ryzen 7000 Series . Fortunately, I was able to ship it back and get my money back the same day. Your mileage may vary. Just make sure the CPU you're buying is compatible with your system .

Intel Core i5-14600K contact pads.

If you don't want to deal with the headache that comes with buying a used CPU, consider purchasing a new CPU from an older generation. You can realistically go one, two, or even three CPU generations back in time and still get a processor that can handle modern games and typical office workloads. These older CPUs typically provide 70–90% of the performance of the latest-gen CPU at a fraction of the price.

My current favorite CPUs that provide excellent value for the money are the following models:

  • Intel Core i5-12400 ($137)
  • AMD Ryzen 5 5600 ($126)
  • AMD Ryzen 5 5500 ($87)
  • Intel Core i3-12100F ($84)

All of these models are perfectly capable of handling gaming and office work. They're two or three years old, so they're in high supply and readily available at most retailers. This is because people buying new CPUs and computers want the latest and greatest, not realizing that they could get a much better deal on an older CPU.

Did you know that you can now buy some CPU models without the stock cooler? Aftermarket CPU coolers have trickled down from the enthusiast market to the mainstream, so AMD and Intel sell CPUs without the stock cooler at a slightly lower price. This is common with high-end CPUs, but some cheaper models are also available without a cooler, like the AMD Ryzen 5 7600X and Intel Core i5-12600K .

A large air CPU cooler is being installed onto a motherboard.

Now, whether a CPU with or without a cooler is a better deal is up to you. If you already have a compatible aftermarket cooler or plan to buy one, it makes sense to skip the cooler. However, if you have no plans of upgrading or buying a cooler separately, a CPU with a stock cooler is often your best option, as you'd have to spend an extra $20–40 plus shipping to get a mediocre CPU cooler.

Unless you're buying a new CPU for an existing computer, don't pay too much attention to whether you're getting AMD or Intel. Both CPU manufacturers have a rich selection of amazing CPUs, so disregarding either will halve your options for no good reason.

AMD CPUs used to be better valued because their CPUs cost less and had better cross-generational motherboard compatibility, but Intel has caught up in both areas thanks to aggressively priced CPUs and BIOS updates on old motherboards.

Instead of looking at the brand, make a list of all CPUs that fall within your budget. Look at some CPU benchmarks relevant to your use case (e.g. gaming or productivity), and buy the CPU that performs the best. Of course, if the price and performance difference is minimal, you have the luxury of choice. Also, don't forget about CPU temperatures and power draw when looking at benchmarks!

MSI Geforce RTX Graphics card

If you plan on using a dedicated GPU, you don't really need integrated graphics . Just like with stock CPU coolers, both AMD and Intel offer CPUs that come without integrated graphics. You can identify these models by the "F" suffix in their names. It's worth noting that some CPUs don't have integrated graphics, but they lack the "F" suffix, like the AMD Ryzen 5000 Series and older, so check the product description.

Conversely, if you're building an office PC and don't need a powerful GPU, get a CPU with integrated graphics, as it's significantly cheaper than a dedicated GPU. CPUs with integrated GPUs have the "G" suffix, but just like the "F" situation, not all of them have the letter, which means you have to check the specs online. AMD uses "G" for its APUs , whereas Intel seems to have retired the suffix in desktop CPUs for the time being.

If you need a motherboard, CPU cooler, or some other random bits of hardware along with the CPU, bundles are a great way to save some cash. CPU+motherboard pairings in particular are quite popular among online retailers, so it's always worth checking the deals before you make a decision. For example, Newegg has a "Combo Up" section that allows me to bundle items together and maximize my savings.

A combo deal for the Ryzen 7 5700G on Newegg.

Just make sure that the deal you're getting through the bundle is actually saving you money. In addition to bundles, pay attention to sales. Retailers frequently run random sales. So, keep an eye on CPU prices with a price tracker if you're not in a hurry to build a new system.

It's a good idea to account for future-proofing when building a new system. This simply means that you have a way to upgrade parts of your PC without changing the whole system; you can keep the motherboard, power supply, RAM, fans, storage, etc.

For example, if you're building an AMD system, it could make more sense to buy a Ryzen 7000 Series CPU and AM5 motherboard than a previous-gen Ryzen 5000 Series and AM4 motherboard. Even though you're paying slightly more for the AM5 CPU and motherboard today, you'll have a clear upgrade path when the next generation of Ryzen CPUs drops.

CPU Chip on an MSI Motherboard

All it takes is a simple BIOS update , and your existing system will be ready for a new generation of CPUs. Just note that not all motherboards and CPUs are compatible just because they use the same socket, so do some research before making the final decision.

Buying a new CPU is never easy, but hopefully, I've cleared up some misconceptions. If you want to get the best value for your money, it's worth doing some research to see what CPU is the best within your budget. Lastly, don't forget to account for future-proofing as well if you plan to upgrade the system over the following years.

Home Resource Library Technical Articles Understanding Multidrop Address Assignments for Thermal Sensors

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Understanding Multidrop Address Assignments for Thermal Sensors

Mar 28 2014

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Author's Contact Information

In many thermal applications, it may be desired to utilize multiple temperature sensors, placed in different physical locations, to monitor the operating temperatures in predefined 'zones' within the system. To accommodate this desire, many thermal products have the added flexibility of user-defined slave addressing.

A similar version was published in the March 2014 issue of Electronics Maker magazine.

Traditionally, most ICs incorporating the Philips ® I 2 C I/O protocol have a fixed (factory-defined) slave address for use during communications. In many thermal applications, however, it may be desirable to utilize multiple temperature sensors, placed in different physical locations, to monitor the operating temperatures in predefined "zones" within the system. To accommodate this while minimizing CPU resources allocated for communications functions, many thermal products have the added flexibility of user-defined slave addressing. This user-defined function uses an additional input pin (or pins) that allows mapping of a specific sensor to a schematically defined slave address.

Categorizing the thermal products by its I/O multidrop capability results in three fundamental variations of the options for user-defined slave addressing:

Input-Level Defined. The condition of the address input pin can be controlled by a simple hardware definition (i.e., resistor placement) or by a dynamic CPU resource. Standard digital logic input levels (V IH /V IL ) utilized on SCL and SDA can also be applied to the address input pin(s).

Figure 1 depicts a typical I 2 C resistor pullup scheme where the I 2 C master's resource is defined as open drain, and the default ADD pin state is Logic 1. The desired decode (ADD input bias) must be presented prior to the associated START signal whenever this slave is to be accessed; it should remain stable until after the associated STOP has been issued.

Figure 1. Input-level-defined addressing as implemented in the DS1621 , DS75 , or MAX6634 temp sensors. When this function is used, then multiple temperature devices like these can have their own slave address.

Input-level-defined components actively decode the address input pin(s) bias to determine the present slave address. On devices with an optional ADD pin to decode states of SDA or SCL, it is recommended that ADD be directly connected to that desired pin. Maximum signal margin is achieved by using full-rail address pin conditioning. When defining the address pin(s) conditions in hardware, use low-ohmic-value pullup/pulldown resistors (< 1kΩ).

Pin-State Defined. The address input pin condition must be controlled by the hardware definition (at PCB assembly). The components in this category have three or more variations of possible slave addresses, including a unique decode for cases where the input pin(s) may be left in an unconnected condition.

Figure 2 depicts a typical I 2 C address pin definition to ground. If ADD is to be defined by a power supply, the pin should be directly connected to the desired supply rail. (Use 0Ω to either V+ or GND.)

Figure 2. Pin-state-defined addressing, as implemented in the MAX6650 or MAX6681 temperature sensors, allows for definition of the address pin with local, direct connections.

Pins defined for "No Connection" should not have any external components or traces contacting those input pads. Figure 3 shows an improper placement of a resistor-divider, here attempting to hold the ADD input at (V+/2). If this pin conditioning is selected, be aware that downstream assembly artifacts (e.g., flux residue, moisture, adjacent digital traces, etc.) can negatively impact the operation of the intended address decoding. Use this unconnected option when there is no other choice available.

Figure 3. Do not use pullup or pulldown resistors on a "No Connection" pin configuration.

Pin-state-defined components operate similar to the input-level-defined designs, with the added complexity of a third (or sometimes fourth) variation of input conditioning (e.g., a float, resistor to GND, etc.). The components in this category are, therefore, much more sensitive to potential address miss-selection, noise coupling from adjacent traces, assembly processing (e.g., surface leakage paths from residual contaminants), or changes in raw silicon processing.

Pins defined to decode a high logic level should be directly connected (i.e., 0Ω to the device power supply. Pins defined to decode a low logic level should be directly connected (i.e., 0Ω to the board ground. Pins defined to decode a resistor to GND may require 5% external component tolerancing. Refer to the product's specifications for more details.

Ordering Defined. A specific ordering variant (i.e., a specific variation of a part's build of materials, BOM) is required so each unique slave address can be utilized. The advantage in this part-number-specific approach is noise immunity in the application. There may also be a disadvantage in the increased procurement/assembly complexity due to handling placement-critical variations of the same chip.

Figure 4 depicts a simplified connection scheme utilizing eight unique DS1775 digital thermometer ordering variants.

Figure 4. Ordering-defined addressing is implemented in the DS1775 and MAX6697 temperature sensors.

The ordering-defined components provide the most electrically robust solution for multichip placements, as there are no additional package pins or signals that must be controlled. But as initially noted, this solution requires a unique BOM and placement requirement on a per-socket basis.

In summary, the need for multidrop thermal sensing is based upon the specific system's temperature-monitoring requirements and a general desire to minimize the CPU resources dedicated to intercomponent I/O. We discussed three variations of multidrop implementations that are available in several temperature sensors and digital thermometers and thermostats offered in Maxim's Thermal Management product line.We also provided some guidance on implementation concerns for each variation.

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